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EXPONENTIAL TECHN INC

Overview
  • Total Patents
    34
About

EXPONENTIAL TECHN INC has a total of 34 patent applications. Its first patent ever was published in 1994. It filed its patents most often in United States. Its main competitors in its focus markets computer technology, semiconductors and measurement are SYNOPSYS TAIWAN CO LTD, TELAIRITY SEMICONDUCTOR INC and P4TENTS1 LLC.

Patent filings in countries

World map showing EXPONENTIAL TECHN INCs patent filings in countries
# Country Total Patents
#1 United States 34

Patent filings per year

Chart showing EXPONENTIAL TECHN INCs patent filings per year from 1900 to 2020

Focus industries

Top inventors

# Name Total Patents
#1 Blomgren James S 24
#2 Cohen Earl T 15
#3 Richter David E 9
#4 Pattin Jay C 6
#5 Buckley Iii Frederick 2
#6 Thusoo Shalesh 2
#7 Wiedmann Siegfried 2
#8 Tilleman Russell W 2
#9 Brashears Cheryl S 2
#10 Brashears Cheryl Senter 2

Latest patents

Publication Filing date Title
US5757690A Embedded ROM with RAM valid bits for fetching ROM-code updates from external memory
US5745913A Multi-processor DRAM controller that prioritizes row-miss requests to stale banks
US5692152A Master-slave cache system with de-coupled data and tag pipelines and loop-back
US5781457A Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU
US5732209A Self-testing multi-processor die with internal compare points
US5784590A Slave cache having sub-line valid bits updated by a master cache
US5751614A Sign-extension merge/mask, rotate/shift, and boolean operations executed in a vectored mux on an ALU
US5687336A Stack push/pop tracking and pairing in a pipelined processor
US5809272A Early instruction-length pre-decode of variable-length instructions in a superscalar processor
US5685009A Shared floating-point registers and register port-pairing in a dual-architecture CPU
US5633819A Inexact leading-one/leading-zero prediction integrated with a floating-point adder
US5652872A Translator having segment bounds encoding for storage in a TLB
US5884057A Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor
US5664159A Method for emulating multiple debug breakpoints by page partitioning using a single breakpoint register
US5634118A Splitting a floating-point stack-exchange instruction for merging into surrounding instructions by operand translation
US5477489A High-stability CMOS multi-port register file memory cell with column isolation and current-mirror row line driver
US5548545A Floating point exception prediction for compound operations and variable precision using an intermediate exponent bus
US5542059A Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order
US5644752A Combined store queue for a master-slave cache system
US5574677A Adaptive non-restoring integer divide apparatus with integrated overflow detect