|
US2013275651A1
|
|
System and method of adjusting a programming step size for a block of a memory
|
|
US2013238955A1
|
|
System and method to decode data subject to a disturb condition
|
|
US2013223151A1
|
|
System and method of determining a programming step size for a word line of a memory
|
|
US2013159766A1
|
|
Wear leveling of multiple memory devices
|
|
US2013003480A1
|
|
Smart bridge for memory core
|
|
US2012084622A1
|
|
System and method of data encoding
|
|
US2013073924A1
|
|
Data storage device and method to correct bit values using multiple read voltages
|
|
US2012102379A1
|
|
System and method of interleaving data according to an adjustable parameter
|
|
US2012204077A1
|
|
Data recovery using additional error correction coding data
|
|
US2012110417A1
|
|
Hybrid error correction coding to address uncorrectable errors
|
|
US2011185251A1
|
|
System and method to correct data errors using a stored count of bit values
|
|
US2010332943A1
|
|
Method and device for selectively refreshing a region of a memory of a data storage device
|
|
US2010332923A1
|
|
System and method responsive to a rate of change of a performance parameter of a memory
|
|
US2010332949A1
|
|
System and method of tracking error data within a storage device
|
