|
US2013219146A1
|
|
Method, device and system for a configurable address space for non-volatile memory
|
|
US2013219105A1
|
|
Method, device and system for caching for non-volatile memory device
|
|
US2012026802A1
|
|
Managed hybrid memory with adaptive power supply
|
|
US2010202194A1
|
|
Dynamically allocable regions in non-volatile memories
|
|
US8254199B1
|
|
Multi-channel memory and power supply-driven channel selection
|
|
US8392683B1
|
|
Dynamic range unlock or lock memory device and method to operate the same
|
|
US8130550B1
|
|
Memory with sub-blocks
|
|
US8230196B1
|
|
Configurable partitions for non-volatile memory
|
|
US2010293317A1
|
|
PCM memories for storage bus interfaces
|
|
CN101889313A
|
|
Non-volatile memory with extended operating temperature range
|
|
US2010157718A1
|
|
Configurable latching for asynchronous memories
|
|
US2010153820A1
|
|
Memory with guard value dependent error correction
|
|
US2007103973A1
|
|
Memory architecture
|
