|
US2013207702A1
|
|
Edge selection techniques for correcting clock duty cycle
|
|
US2013257483A1
|
|
Sense amplifier-type latch circuits with static bias current for enhanced operating frequency
|
|
US2013214865A1
|
|
Capacitive level-shifting circuits and methods for adding DC offsets to output of current-integrating amplifier
|
|
US2013207722A1
|
|
Peaking amplifier with capacitively-coupled parallel input stages
|
|
US2012153910A1
|
|
Dual-loop voltage regulator architecture with high DC accuracy and fast response time
|
|
US2012314721A1
|
|
Timing recovery method and apparatus for an input/output bus with link redundancy
|
|
US2012106687A1
|
|
Calibration of multiple parallel data communications lines for high skew conditions
|
|
US2010202506A1
|
|
Circuits and methods for DFE with reduced area and power consumption
|
|
US2009252215A1
|
|
Sampled current-integrating decision feedback equalizer and method
|
|
US2009244958A1
|
|
Hybrid superconducting-magnetic memory cell and array
|
