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Latch Circuit Preventing Failed Output In Case That Input Signal and Control Signal Happen to Transit Almost at Once
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Data Buffer Capable of Compensating Data Skew on Common Data Bus and Buffering Method thereof
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Data Buffer Capable of Compensating Data Skew on Common Data Bus and Buffering Method thereof
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Exclusive OR Logic Circuit
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Flip Flop Circuit with High Speed and Low Power
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Buffer for Bidirectional Common Bus and Bus Circuit Comprising the Buffers
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Supply Voltage Level Shifter
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Flip Flop Circuit with Low Power and High Speed
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Memory Comprising Cell with Low Power and High Speed
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Common Data Bus Circuit and Integrated Circuit Including Said Common Data Bus
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Circuit and Method for Generating Control Signal for Static RAM, and Static RAM Comprising the same Circuit
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The sensor module detecting target over 3-dimension
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The sensor module detecting target over 3-dimension
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Differential signal generator
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Apparatus for detecting errors of clock signal and signal processor comprising the same
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Self biased differential amplifier with wide common mode input voltage range and input buffer
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Voltage controlled oscillator and voltage controlled delay line
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Voltage controlled oscillator
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