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BASKER VEERARAGHAVAN S

Overview
  • Total Patents
    38
About

BASKER VEERARAGHAVAN S has a total of 38 patent applications. Its first patent ever was published in 2007. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors, surface technology and coating and micro-structure and nano-technology are HOUJIYOU TETSUYA, ARVIN CHARLES L and HUA HONG SEMICONDUCTOR WUXI LTD.

Patent filings in countries

World map showing BASKER VEERARAGHAVAN Ss patent filings in countries
# Country Total Patents
#1 United States 38

Patent filings per year

Chart showing BASKER VEERARAGHAVAN Ss patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Basker Veeraraghavan S 38
#2 Yamashita Tenko 17
#3 Yeh Chun-Chen 11
#4 Leobandung Effendi 9
#5 Standaert Theodorus E 7
#6 Bu Huiming 7
#7 Cheng Kangguo 6
#8 Furukawa Toshiharu 5
#9 Deligianni Hariklia 5
#10 Koburger Iii Charles W 5

Latest patents

Publication Filing date Title
US2014087526A1 Multi-gate field effect transistor devices
US2014061734A1 Finfet with reduced parasitic capacitance
US2014054705A1 Silicon germanium channel with silicon buffer regions for fin field effect transistor device
US2014038382A1 Structure and method to realize conformal doping in deep trench applications
US2014030864A1 Method of eDRAM DT strap formation in FinFET device structure
US2013175594A1 Integrated circuit including DRAM and SRAM/logic
US8569152B1 Cut-very-last dual-epi flow
US2013316513A1 Fin isolation for multigate transistors
US8557657B1 Retrograde substrate for deep trench capacitors
US2013181261A1 Borderless contact structure
US2013161744A1 finFET with merged fins and vertical silicide
US8445334B1 SOI FinFET with recessed merged Fins and liner for enhanced stress coupling
US2013087841A1 Embeded DRAM cell structures with high conductance electrodes and methods of manufacture
US2012280250A1 Spacer as hard mask scheme for in-situ doping in CMOS finFETs
US2012181613A1 Methods for Forming Field Effect Transistor Devices With Protective Spacers
US2012070947A1 Inducing stress in fin-fet device
US2011101455A1 FinFET spacer formation by oriented implantation
US2010009131A1 Multi-exposure lithography employing a single anti-reflective coating layer
US2009127121A1 Method and apparatus for electroplating on soi and bulk semiconductor wafers
US2009121343A1 Carbon nanotube structures for enhancement of thermal dissipation from semiconductor modules