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APLUS FLASH TECHNOLOGY INC

Overview
  • Total Patents
    188
  • GoodIP Patent Rank
    139,299
About

APLUS FLASH TECHNOLOGY INC has a total of 188 patent applications. Its first patent ever was published in 1997. It filed its patents most often in United States, WIPO (World Intellectual Property Organization) and Taiwan. Its main competitors in its focus markets computer technology, semiconductors and electrical machinery and energy are HAN JINMAN, HANZAWA SATORU and NEXFLASH TECHNOLOGIES INC.

Patent filings per year

Chart showing APLUS FLASH TECHNOLOGY INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Hsu Fu-Chang 133
#2 Lee Peter W 104
#3 Tsao Hsing-Ya 81
#4 Lee Peter Wung 68
#5 Ma Han-Rei 26
#6 Hsu Fu Chang 8
#7 Chen Hung-Sheng 8
#8 Wang Kesheng 8
#9 Chan Vei-Han 8
#10 Lee Peter 7

Latest patents

Publication Filing date Title
WO2016048846A1 Self-timed slc nand pipeline and concurrent program without verification
WO2016028717A1 Vsl-based vt-compensation and analog program scheme for nand array without csl
WO2016014731A1 Yukai vsl-based vt-compensation for nand memory
WO2015100434A2 A HYBRID NAND WITH ALL-BL m-PAGE OPERATION SCHEME
US2015078086A1 Multi-task concurrent/pipeline NAND operations on all planes
US2015078080A1 NAND array hiarchical BL structures for multiple-WL and all-BL simultaneous erase, erase-verify, program, program-verify, and read operations
WO2014210424A2 Novel nand array architecture for multiple simultaneous program and read
US2014119120A1 NVSRAM cells with voltage flash charger
US2014119119A1 Pseudo-8T NVSRAM cell with a charge-follower
US2014119118A1 8T NVSRAM cell and cell operations
US2014112072A1 10T NVSRAM cell and cell operations
US2014104946A1 On-chip HV and LV capacitors acting as the second back-up supplies for NVSRAM auto-store operation
US2014347933A1 NOR-based BCAM/TCAM cell and array with NAND scalability
US2013279251A1 Shielding 2-cycle half-page read and program schemes for advanced NAND flash design
US2013272067A1 Non-boosting program inhibit scheme in NAND design
US2013182509A1 1T1b and 2T2b flash-based, data-oriented EEPROM design
WO2013075067A1 Low voltage page buffer for use in nonvolatile memory design
WO2012103075A1 An one-die flotox-based combo non-volatile memory
WO2012036751A2 Different types of memory integrated in one chip by using a novel protocol
WO2012036739A2 An eeprom-based, data-oriented combo nvm design