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LEE PETER WUNG

Overview
  • Total Patents
    45
  • GoodIP Patent Rank
    123,586
  • Filing trend
    0.0%
About

LEE PETER WUNG has a total of 45 patent applications. It increased the IP activity by 0.0%. Its first patent ever was published in 1998. It filed its patents most often in United States, China and Japan. Its main competitors in its focus markets computer technology, semiconductors and environmental technology are HAN JINMAN, PERNER FREDERICK and MULTI LEVEL MEMORY TECHNOLOGY.

Patent filings in countries

World map showing LEE PETER WUNGs patent filings in countries

Patent filings per year

Chart showing LEE PETER WUNGs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Lee Peter Wung 45
#2 Hsu Fu-Chang 25
#3 Tsao Hsing-Ya 9
#4 Kyo Fusho 1
#5 Wang Kesheng 1
#6 Ma Han-Rei 1
#7 So Koa 1

Latest patents

Publication Filing date Title
US2019018778A1 Hierarchical nand memory device capable of performing concurrent and pipeline operations
US2017352424A1 Plural Distributed PBS with Both Voltage and Current Sensing SA for J-Page Hierarchical NAND Array's Concurrent Operations
US2016314833A1 Partial/full array/block erase for 2D/3D hierarchical NAND
CN107924699A Part/complete array/block erasing for 2D/3D hierarchy types NAND
US2016172037A1 Novel lv nand-cam search scheme using existing circuits with least overhead
US2016099047A1 Multi-task concurrent/pipeline NAND operations on all planes
US2014347928A1 Low disturbance, power-consumption, and latency in NAND read and program-verify operations
US2014085978A1 Method and architecture for improving defect detectability, coupling area, and flexibility of NVSRAM cells and arrays
US2013294161A1 Low-voltage fast-write nvsram cell
US2013215683A1 Three-Dimensional Flash-Based Combo Memory and Logic Design
US2012176841A1 Flexible 2T-based fuzzy and certain matching arrays
US2012155173A1 Universal timing waveforms sets to improve random access read and write speed of memories
US2012069651A1 EEPROM-based, data-oriented combo NVM design
US2012063233A1 EEPROM-based, data-oriented combo NVM design
US2012087190A1 Write bias condition for 2T-string NOR flash cell
US2012020157A1 Novel high-temperature non-volatile memory design
US2012001233A1 Embedded NOR flash memory process with NAND cell and true logic compatible low voltage device
US2011267883A1 DRAM-like NVM memory array and sense amplifier design for high temperature and high endurance operation
US2012195123A1 Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory
US2011157974A1 Cell array for highly-scalable, byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory