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Fpga ram blocks optimized for use as register files
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Clustered field programmable gate array architecture
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Field programmable gate array architecture having Clos network-based input interconnect
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Inverting flip-flop for use in field programmable gate arrays
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(N+1) input flip-flop packing with logic in FPGA architectures
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Single event transient mitigation and measurement in integrated circuits
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Push-pull memory cell configured for simultaneous programming of n-channel and p-channel non-volatile transistors
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Programmable logic device with programmable wakeup pins
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PLD providing soft wakeup logic
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Push-pull FPGA cell
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Circuits and methods for testing FPGA routing switches
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Reduced-edge radiation-tolerant non-volatile transistor memory cells
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Quadratic and cubic compensation of sigma-delta D/A and A/D converters
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Split gate memory cell for programmable circuit device
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Programmable delay line compensated for process, voltage, and temperature
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Staggered I/O groups for integrated circuits
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Radiation-tolerant flash-based FPGA memory cells
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Logic module including versatile adder for FPGA
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High-voltage dual-polarity I/O p-well pump ESD protection circuit
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Programmable logic device with a microcontroller-based control system
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