WO0111687A1
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Gate isolated triple-well non-volatile cell
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Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resources
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Output buffer for making a high voltage (5.0 volt) compatible input/output in a low voltage (2.5 volt) semiconductor process
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Inversion of product term line before or logic in a programmable logic device (PLD)
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Zero-power CMOS non-volatile memory cell having an avalanche injection element
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Non-volatile memory cell having dual avalanche injection elements
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Triple-well EEPROM cell using P-well for tunneling across a channel
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Floating gate memory apparatus and method for selected programming thereof
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Gate insulator process for nanometer MOSFETS
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Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench
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Boron doped silicon capacitor plate
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Avalanche injection EEPROM memory cell with P-type control gate
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Band gap reference using a low voltage power supply
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High voltage detector to control a power supply voltage pump for a 2.5 volt semiconductor process device
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Non-volatile memory device having a high-reliability composite insulation layer
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Fabrication of oxide regions having multiple thicknesses using minimized number of thermal cycles
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Method for sorting semiconductor devices having a plurality of non-volatile memory cells
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Two transistor EEPROM cell
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Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress
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Two transistor EEPROM cell using P-well for tunneling across a channel
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