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ROM segmented bitline circuit
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Multi-chip packaged function including a programmable device and a fixed function die and use for application acceleration
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Structured integrated circuit device with multiple configurable via layers
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Multiple write during simultaneous memory access of a multi-port memory device
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Via-configurable high-performance logic block involving transistor chains
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Temperature Controlled Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node
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Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller
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Via-configurable high-performance logic block involving transistor chains
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Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface
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Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node
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Microcontroller controlled or direct mode controlled network-fabric on a structured ASIC
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Via-configurable high-performance logic block architecture
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Programming and circuit topologies for programmable vias
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Configurable write policy in a memory system
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Dynamic phase alignment
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Single via structured IC device
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Structured integrated circuit device
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Customizable power and ground pins
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Programmable via modeling
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BRPI0513689A
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semiconductor devices, logic assemblies and semiconductor wafers
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