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Integrated circuit computing device and computing processing system
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Digital delay phase-locked loop and locking method thereof
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Integrated circuit computing device and computing processing system
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Self-adaptive and calibrated ODT (on-die termination) circuit applied to FPGA (field programmable Gate array)
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Bidirectional MIPI interface circuit based on FPGA universal interface and operation method thereof
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A kind of wide same or circuit optimization method
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A kind of ram test method and test device
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A kind of MUX tree logical construction optimization method, module and storage medium
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A kind of dual loop phase-locked loop analog core circuit and phaselocked loop applied to FPGA
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A kind of width XOR circuit optimization method
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A kind of phase-locked loop apparatus and fpga chip applied to fpga chip
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A kind of real-time debugging system of FPGA on piece and method
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A kind of FPGA and its system supporting more bit stream downloadings
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A kind of method and system automatically updating placement-and-routing based on FPGA
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A kind of chip detecting method based on FPGA/MCU
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A kind of test board of the CPLD chip based on FPGA/MCU
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A method of test RAM
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A kind of storage control based on FPGA
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A kind of SOC chip and embedded system of integrated dual processor
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A kind of frequency measurement method and its measuring system
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