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WARREN ROBERT W

Overview
  • Total Patents
    23
About

WARREN ROBERT W has a total of 23 patent applications. Its first patent ever was published in 2007. It filed its patents most often in United States. Its main competitors in its focus markets computer technology, semiconductors and telecommunications are RENESAS ELECTRONICS CORP, GLOBALFOUNDRIES INC and HSU LOUIS L.

Patent filings in countries

World map showing WARREN ROBERT Ws patent filings in countries
# Country Total Patents
#1 United States 23

Patent filings per year

Chart showing WARREN ROBERT Ws patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Warren Robert W 23
#2 Rossi Nic 12
#3 Al-Refaee Fadi Afa 4
#4 Haddad Stephen N 4
#5 Bahram Nikolai K 4
#6 Lee Hyun Jung 3
#7 Mankin Robb 2
#8 Li Jianjun 1
#9 Holt Buddy Scott 1

Latest patents

Publication Filing date Title
US2013208424A1 Solid via pins for improved thermal and electrical conductivity
US2013087915A1 Copper Stud Bump Wafer Level Package
US2013062742A1 Spot plated leadframe and IC bond pad via array design for copper wire
US2013034990A1 Shielded USB connector module with molded hood and LED light pipe
US2012326304A1 Externally Wire Bondable Chip Scale Package in a System-in-Package Module
US2012286408A1 Wafer level package with thermal pad for higher power dissipation
US2012241954A1 Unpackaged and packaged IC stacked in a system-in-package module
US2012188738A1 Integrated led in system-in-package module
US2012119341A1 Semiconductor packages with reduced solder voiding
US2012104591A1 Systems and methods for improved heat dissipation in semiconductor packages
US2012032350A1 Systems and Methods for Heat Dissipation Using Thermal Conduits
US2011058422A1 Systems and methods for circular buffering control in a memory device
US2011060967A1 Systems and methods for re-designating memory regions as error code corrected memory regions
US2011058415A1 Systems and methods for increasing bit density in a memory cell
US2011060861A1 Systems and methods for variable level use of a multi-level flash memory
US2011058421A1 Systems and methods for peak power and/or EMI reduction
US2010213590A1 Systems and methods of tamper proof packaging of a semiconductor device
US2011060886A1 Systems and methods for selecting bit per cell density of a memory cell based on data typing
US2011185111A1 Systems and methods for extended life multi-bit memory cells