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TEXAS INSTR ACER INC

Overview
  • Total Patents
    134
About

TEXAS INSTR ACER INC has a total of 134 patent applications. Its first patent ever was published in 1996. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors, machines and micro-structure and nano-technology are MAGEPOWER SEMICONDUCTOR CORP, EPITACTIX PTY LTD and FURUKAWA TOSHIHARU.

Patent filings in countries

World map showing TEXAS INSTR ACER INCs patent filings in countries
# Country Total Patents
#1 United States 134

Patent filings per year

Chart showing TEXAS INSTR ACER INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Wu Shye-Lin 129
#2 Wu Shye Lin 1
#3 Liu Hsin-Tang 1
#4 Lee Cheng-Nan 1
#5 Wu Tsu Chu 1
#6 Gau Jiahn-Rong 1
#7 Jan Cheng-Geng 1
#8 Wu Tsun-Chu 1
#9 Hsu Peter K Y 1
#10 Hsu Peter Kuo-Yuan 1

Latest patents

Publication Filing date Title
US6294797B1 MOSFET with an elevated source/drain
US6190977B1 Method for forming MOSFET with an elevated source/drain
US6214696B1 Method of fabricating deep-shallow trench isolation
US6171893B1 Method for forming self-aligned silicided MOS transistors with ESD protection improvement
US6265259B1 Method to fabricate deep sub-μm CMOSFETs
US6127712A Mosfet with buried contact and air-gap gate structure
US6162681A DRAM cell with a fork-shaped capacitor
US6117756A Method of forming high density and low power flash memories with a high capacitive-coupling ratio
US6316316B1 Method of forming high density and low power flash memories with a high capacitive-coupling ratio
US6207505B1 Method for forming high density nonvolatile memories with high capacitive-coupling ratio
US6255167B1 Method of forming high density buried bit line flash EEPROM memory cell with a shallow trench floating gate
US6548362B1 Method of forming MOSFET with buried contact and air-gap gate structure
US6133104A Method of eliminating buried contact trench in MOSFET devices with self-aligned silicide including a silicon connection to the buried contact region which comprises a doped silicon sidewall
US6211556B1 Eliminating buried contact trench in MOSFET devices having self-aligned silicide
US6204124B1 Method for forming high density nonvolatile memories with high capacitive-coupling ratio
US6156613A Method to form MOSFET with an elevated source/drain
US6294416B1 Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts
US6177323B1 Method to form MOSFET with an elevated source/drain for PMOSFET
US6265263B1 Method for forming a DRAM capacitor with porous storage node and rugged sidewalls
US6211002B1 CMOS process for forming planarized twin wells