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Switching speed improvement in DMO by implanting lightly doped region under gate
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Double gate-oxide for reducing gate-drain capacitance in trenched DMOS with high-dopant concentration buried-region under trenched gate
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Gate/drain capacitance reduction for double gate-oxide DMOS without degrading avalanche breakdown
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Cell density improvement in planar DMOS with farther-spaced body regions and novel gates
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MOSFET device to reduce gate-width without increasing JFET resistance
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Semiconductor cell array with high packing density
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Enhancing DMOS device ruggedness by reducing transistor parasitic resistance and by inducing breakdown near gate runners and termination area
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MOSFET power device manufactured with reduced number of masks by fabrication simplified processes
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Method of forming a semiconductor structure with uniform threshold voltage and punch-through tolerance
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DMOS transistors with diffusion merged body regions manufactured with reduced number of masks and enhanced ruggedness
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Trenched DMOS device provided with body-dopant redistribution-compensation region for preventing punch through and adjusting threshold voltage
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Method of forming a semiconductor structure having reduced threshold voltage and high punch-through tolerance
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Method of forming a semiconductor structure having laterally merged body layer
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Power MOSFETs and cell topology
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