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SPIN TRANSFER TECH INC

Overview
  • Total Patents
    97
  • GoodIP Patent Rank
    14,734
  • Filing trend
    ⇩ 20.0%
About

SPIN TRANSFER TECH INC has a total of 97 patent applications. It decreased the IP activity by 20.0%. Its first patent ever was published in 2015. It filed its patents most often in United States, WIPO (World Intellectual Property Organization) and China. Its main competitors in its focus markets computer technology, semiconductors and electrical machinery and energy are ADESTO TECH CORP, ADESTO TECHNOLOGIES CORP and INSTON INC.

Patent filings per year

Chart showing SPIN TRANSFER TECH INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Berger Neal 38
#2 Pinarbasi Mustafa Michael 23
#3 Louie Benjamin 23
#4 El Baraji Mourad 20
#5 Crudele Lester 20
#6 Kardasz Bartlomiej Adam 20
#7 Pinarbasi Mustafa 18
#8 El-Baraji Mourad 17
#9 Hillman Daniel 14
#10 Louie Benjamin Stanley 14

Latest patents

Publication Filing date Title
WO2019133299A1 A memory device with a dual y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank
WO2019133293A1 A memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register
WO2019133244A1 Smart cache design to prevent overflow for a memory device with a dynamic redundancy register
WO2019133233A1 A method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device
WO2019133223A1 A method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device
WO2019133213A1 A method of processing incompleted memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register
US2020185601A1 Method for manufacturing a data recording system utilizing heterogeneous magnetic tunnel junction types in a single chip
US2019295618A1 Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer
US2019296224A1 Magnetic Tunnel Junction Devices Including a Free Magnetic Trench Layer and a Planar Reference Magnetic Layer
US2019296230A1 Methods of Manufacturing Three-Dimensional Arrays with MTJ Devices Including a Free Magnetic Trench Layer and a Planar Reference Magnetic Layer
US2020052034A1 Magnetic tunnel junction memory element with improved reference layer stability for magnetic random access memory application
US10411185B1 Process for creating a high density magnetic tunnel junction array test platform
US2019280194A1 Magnetic tunnel junction wafer adaptor used in magnetic annealing furnace and method of using the same
US10388861B1 Magnetic tunnel junction wafer adaptor used in magnetic annealing furnace and method of using the same
US2019214429A1 Devices including magnetic tunnel junctions integrated with selectors
US10186551B1 Buried tap for a vertical transistor used with a perpendicular magnetic tunnel junction (PMTJ)
US2019214430A1 Methods of fabricating magnetic tunnel junctions integrated with selectors
US10186308B1 Magnetic random access memory having improved reliability through thermal cladding
US10211395B1 Method for combining NVM class and SRAM class MRAM elements on the same chip
US2019207108A1 Method for manufacturing magnetic tunnel junction pillars using photolithographically directed block copolymer self-assembly and organometallic gas infusion