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Re-writable resistance-switching memory with balanced series stack
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Temperature compensation of conductive bridge memory arrays
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Single device driver circuit to control three-dimensional memory element array
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Capacitive discharge method for writing to non-volatile memory
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Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography
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Storage sub-system for a computer comprising write-once memory devices and write-many memory devices and related method
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Mixed-use memory array
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Mixed-use memory array with different data states
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TFT charge storage memory cell having high-mobility corrugated channel
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