RANADE PUSHKAR has a total of 14 patent applications. Its first patent ever was published in 2004. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors and digital networks are CHEN XIANGDONG, MEGAMOS CORP and KUNSHAN XUYANG ELECTRONIC MATERIALS CO LTD.
# | Country | Total Patents | |
---|---|---|---|
#1 | United States | 14 |
# | Industry | |
---|---|---|
#1 | Semiconductors | |
#2 | Digital networks |
# | Technology | |
---|---|---|
#1 | Semiconductor devices | |
#2 | Digital information transmission |
# | Name | Total Patents |
---|---|---|
#1 | Ranade Pushkar | 14 |
#2 | Lilak Aaron D | 2 |
#3 | Natarajan Sanjay | 2 |
#4 | Maiz Jose | 2 |
#5 | Zawadzki Keith | 2 |
#6 | Zietz Gerard T | 2 |
#7 | Paulson Leif | 2 |
#8 | Sonkusale Sachin R | 2 |
#9 | Shifren Lucian | 2 |
#10 | Okabe Ken-Ichi | 1 |
Publication | Filing date | Title |
---|---|---|
US2012139051A1 | Source/drain extension control for advanced transistors | |
US2012083132A1 | Method for minimizing defects in a semiconductor substrate due to ion implantation | |
US2008237741A1 | Methods of forming improved epi fill on narrow isolation bounded source/drain regions and structures formed thereby | |
US2008237661A1 | Ultra-abrupt semiconductor junction profile | |
US2008227250A1 | CMOS device with dual-epi channels and self-aligned contacts | |
US2008121932A1 | Active regions with compatible dielectric layers | |
US2006084248A1 | Methods of optimization of implant conditions to minimize channeling and structures formed thereby |