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Erasing storage nodes in a bi-directional nonvolatile memory cell
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Refresh operations that change address mappings in a non-volatile memory
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Parallel programming of multiple-bit-per-cell memory cells on a continuous word line
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Bit line reference circuits for binary and multiple-bit-per-cell memories
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Bi-directional floating gate nonvolatile memory
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Flash memory array partitioning architectures
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Contactless flash memory with shared buried diffusion bit line architecture
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Contactless flash memory with buried diffusion bit/virtual ground lines
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Data coding for multi-bit-per-cell memories having variable numbers of bits per memory cell
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Flash memory with dynamic refresh
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Sectorless flash memory architecture
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Multi-bit-cell non-volatile memory with maximized data capacity
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Read and write operations using constant row line voltage and variable column line load
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Data management for multi-bit-per-cell memories
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High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations
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