WO2007089558A2
|
|
Method to increase charge retention of non-volatile memory
|
US2006291321A1
|
|
Word line driver for DRAM embedded in a logic process
|
US6795364B1
|
|
Method and apparatus for lengthening the data-retention time of a DRAM device in standby mode
|
US2003147277A1
|
|
Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same
|
US2003067830A1
|
|
Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors
|
US2002105844A1
|
|
Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division
|
US6661042B2
|
|
One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
|
US6686624B2
|
|
Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
|
US2003093744A1
|
|
Error correcting memory and method of operating same
|
US2002094697A1
|
|
DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
|
TW499739B
|
|
Reduced topography dram cell fabricated using a modified logic process and method for operating same
|
US6504780B2
|
|
Method and apparatus for completely hiding refresh operations in a dram device using clock division
|
US6496437B2
|
|
Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory
|
US6468855B2
|
|
Reduced topography DRAM cell fabricated using a modified logic process and method for operating same
|
US6370073B2
|
|
Single-port multi-bank memory system having read and write buffers and method of operating same
|
US6370052B1
|
|
Method and structure of ternary CAM cell in logic process
|
US6442060B1
|
|
High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process
|
WO0050996A1
|
|
Method and apparatus for memory redundancy with no critical delay-path
|
US6732229B1
|
|
Method and apparatus for memory redundancy with no critical delay-path
|
US6329240B1
|
|
Non-volatile memory cell and methods of fabricating and operating same
|