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MONOLITHIC SYSTEM TECH INC

Overview
  • Total Patents
    118
About

MONOLITHIC SYSTEM TECH INC has a total of 118 patent applications. Its first patent ever was published in 1993. It filed its patents most often in United States, WIPO (World Intellectual Property Organization) and EPO (European Patent Office). Its main competitors in its focus markets computer technology, semiconductors and digital networks are MOSYS INC, ZENTEL JAPAN CORP and PYEON HONG BEOM.

Patent filings per year

Chart showing MONOLITHIC SYSTEM TECH INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Leung Wingyu 96
#2 Hsu Fu-Chieh 67
#3 Lee Winston 9
#4 Leung Wing Y 4
#5 Tang Jui-Pin 4
#6 Lin Jeffrey J 3
#7 Sim Jae-Kwang 3
#8 Tam Kit Sang 3
#9 Leung Wing Yu 2
#10 Sinitsky Dennis 2

Latest patents

Publication Filing date Title
WO2007089558A2 Method to increase charge retention of non-volatile memory
US2006291321A1 Word line driver for DRAM embedded in a logic process
US6795364B1 Method and apparatus for lengthening the data-retention time of a DRAM device in standby mode
US2003147277A1 Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same
US2003067830A1 Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors
US2002105844A1 Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division
US6661042B2 One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
US6686624B2 Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
US2003093744A1 Error correcting memory and method of operating same
US2002094697A1 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
TW499739B Reduced topography dram cell fabricated using a modified logic process and method for operating same
US6504780B2 Method and apparatus for completely hiding refresh operations in a dram device using clock division
US6496437B2 Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory
US6468855B2 Reduced topography DRAM cell fabricated using a modified logic process and method for operating same
US6370073B2 Single-port multi-bank memory system having read and write buffers and method of operating same
US6370052B1 Method and structure of ternary CAM cell in logic process
US6442060B1 High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process
WO0050996A1 Method and apparatus for memory redundancy with no critical delay-path
US6732229B1 Method and apparatus for memory redundancy with no critical delay-path
US6329240B1 Non-volatile memory cell and methods of fabricating and operating same