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Two-level cache memory system
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Redundant element substitution apparatus
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Sense amp for bit line sensing and data latching
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Redundancy selection apparatus and method for an array
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Circular scheduling method and apparatus for executing computer programs by moving independent instructions out of a loop
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Low-noise high-speed output buffer and method for controlling same
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Differential bus with specified default value
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Interrupt reporting for single-bit memory errors
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Slot determination mechanism using pulse counting
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Circuit synchronization system
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Processor controlled interface with instruction streaming
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Method and apparatus for precise floating point exceptions
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Computer system
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Functional units for computers
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Write buffer
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Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories
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