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US2013262823A1
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Instruction merging optimization
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US2013262839A1
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Instruction merging optimization
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US2013263153A1
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Optimizing subroutine calls based on architecture level of called subroutine
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US2013262829A1
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Decode time instruction optimization for load reserve and store conditional sequences
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US2013262821A1
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Performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching
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US2013262822A1
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Caching optimized internal instructions in loop buffer
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US2013246768A1
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Transforming non-contiguous instruction specifiers to contiguous instruction specifiers
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US2013212139A1
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Mixed precision estimate instruction computing narrow precision result for wide precision inputs
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US2013179736A1
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Ticket consolidation
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US2013086598A1
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Generating compiled code that indicates register liveness
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US2013086367A1
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Tracking operand liveness information in a computer system and performing function based on the liveness information
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US2013086365A1
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Exploiting an architected list-use operand indication in a computer system operand resource pool
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US2013086362A1
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Prefix computer instruction for compatibily extending instruction functionality
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US2013086368A1
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Using register last use infomation to perform decode-time computer instruction optimization
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US2013086364A1
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Managing a Register Cache Based on an Architected Computer Instruction Set Having Operand Last-User Information
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US2013086361A1
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Scalable decode-time instruction sequence optimization of dependent instructions
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US2013086363A1
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Computer instructions for activating and deactivating operands
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US2013073836A1
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Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers
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US2013073838A1
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Multi-addressable register files and format conversions associated therewith
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US2011296421A1
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Method and apparatus for efficient inter-thread synchronization for helper threads
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