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Cache line use history based done bit modification to D-cache replacement scheme
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Cache line use history based done bit modification to I-cache replacement scheme
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D-cache line use history based done bit based on successful prefetchable counter
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I-cache line use history based done bit based on successful prefetchable counter
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Vector morphing mechanism for multiple processor cores
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structure for early conditional branch resolution
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Design structure for double-width instruction queue for instruction execution
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Design structure for l2 cache/nest address translation
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Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss
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Structure for self prefetching l2 cache mechanism for instruction lines
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Design structure for self prefetching l2 cache mechanism for data lines
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structure for a cascaded delayed execution pipeline
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System and Method for Optimization Within a Group Priority Issue Schema for a Cascaded Pipeline
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System and Method for Resolving Issue Conflicts of Load Instructions
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System and Method for Resolving Issue Conflicts of Load Instructions
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System and method for optimization within a group priority issue schema for a cascaded pipeline
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System and Method for Prioritizing Floating-Point Instructions
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System and Method for Issue Schema for a Cascaded Pipeline
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Butterfly Physical Chip Floorplan to Allow an ILP Core Polymorphism Pairing
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Scalar Processor Instruction Level Parallelism (ILP) Coupled Pair Morph Mechanism
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