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LUE HANG-TING

Overview
  • Total Patents
    31
About

LUE HANG-TING has a total of 31 patent applications. Its first patent ever was published in 2006. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors and computer technology are CHEN FREDERICK T, LIAW JHON JHY and NINGBO ADVANCED MEMORY TECH CORP.

Patent filings in countries

World map showing LUE HANG-TINGs patent filings in countries
# Country Total Patents
#1 United States 31

Patent filings per year

Chart showing LUE HANG-TINGs patent filings per year from 1900 to 2020

Focus industries

Focus technologies

Top inventors

# Name Total Patents
#1 Lue Hang-Ting 31
#2 Hsiao Yi-Hsuan 5
#3 Lai Erh-Kun 4
#4 Chen Shih-Hung 3
#5 Wang Szu-Yu 3
#6 Hsu Tzu-Hsuan 2
#7 Hsu Tzu Hsuan 1
#8 Wang Szu Yu 1
#9 Chang Kuo-Pin 1
#10 Lai Sheng-Chih 1

Latest patents

Publication Filing date Title
US2014231954A1 3D NAND flash memory
US8759899B1 Integration of 3d stacked ic device with peripheral circuits
US2012327719A1 Thermally assisted flash memory with segmented word lines
US2012281478A1 Thermally assisted flash memory with diode strapping
US2012327714A1 Memory Architecture of 3D Array With Diode in Memory String
US2012181654A1 Mufti-layer single crystal 3D stackable memory
US2012281481A1 Thermally assisted dielectric charge trapping flash
US2012182801A1 Memory architecture of 3D NOR array
US2012181684A1 Semiconductor structure and method for manufacturing the same
US2012182807A1 Three-dimensional stacked and-type flash memory structure and methods of manufacturing and operating the same hydride
US2012181580A1 Semiconductor Structure and Manufacturing Method of the Same
US2012147675A1 Nonvolatile stacked NAND memory
US2012020138A1 Transistor having an adjustable gate resistance and semiconductor device comprising the same
US2010176438A1 Depletion-mode charge-trapping flash device
US2010265766A1 Bandgap engineered charge trapping memory in two-transistor nor architecture
US2009262583A1 Floating gate memory device with interpoly charge trapping structure
US2008175053A1 Silicon on insulator and thin film transistor bandgap engineered split gate memory
US2008116506A1 Charge trapping devices with field distribution layer over tunneling barrier
US2008080248A1 Cell operation methods using gate-injection for floating gate NAND flash memory
US2006202261A1 Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays