|
US2021117157A1
|
|
Systems and Methods for Low Latency Modular Multiplication
|
|
US2021117154A1
|
|
Rounding Circuitry for Floating-Point Mantissas
|
|
US2020326948A1
|
|
Systems and Methods for Loading Weights into a Tensor Processing Block
|
|
US8996600B1
|
|
Specialized processing block for implementing floating-point multiplier with subnormal operation support
|
|
US9069624B1
|
|
Systems and methods for DSP block enhancement
|
|
US8898551B1
|
|
Reduced matrix Reed-Solomon encoding
|
|
US9098332B1
|
|
Specialized processing block with fixed- and floating-point structures
|
|
US9164728B1
|
|
Ternary DSP block
|
|
US9032277B1
|
|
Parallel low and asymmetric rate Reed Solomon coding
|
|
US8856201B1
|
|
Mixed-mode multiplier using hard and soft logic circuitry
|
|
US8649518B1
|
|
Implementing CSA cryptography in an integrated circuit device
|
|
US2012054256A1
|
|
Calculation of trigonometric functions in an integrated circuit device
|
|
US8949298B1
|
|
Computing floating-point polynomials in an integrated circuit device
|
|
US8812819B1
|
|
Methods and apparatus for reordering data signals in fast fourier transform systems
|
|
US2012290819A1
|
|
Dsp block with embedded floating point structures
|
|
US8707143B1
|
|
Multiplication-based reed-solomon encoding architecture
|
|
US8482312B1
|
|
Logic structures for ternary addition in logic devices
|
|
US8621331B1
|
|
Continuous parallel cyclic BCH decoding architecture
|
|
US8667045B1
|
|
Generalized parallel counter structures in logic devices
|
|
US8681974B1
|
|
Array encryption core
|
