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Managing state in accelerators
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Self-checking compression
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Scalable application-customized memory compression
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Ultra-secure accelerators
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Atomic instructions for copy-xor of data
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Instruction set architectures for fine-grained heterogeneous processing
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Systems, methods, and apparatuses for compression using hardware and software
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Encrypting Observable Address Information
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Apparatus and method to accelerate compression and decompression operations
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Method for signing and verifying data using multiple hash algorithms and digests in PKCS
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Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction
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Apparatus and method for efficiently executing boolean functions
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Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction
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Bitstream processing using coalesced buffers and delayed matching and enhanced memory writes
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Addition instructions with independent carry chains
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Digest generation
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Rotate instructions that complete execution without reading carry flag
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Multiplication instruction for which execution completes without writing a carry flag
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Add instructions to add three source operands
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System, method, and apparatus for a scalable processor architecture for a variety of string processing applications
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