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KILOPASS TECH INC

Overview
  • Total Patents
    73
  • GoodIP Patent Rank
    20,005
  • Filing trend
    ⇩ 100.0%
About

KILOPASS TECH INC has a total of 73 patent applications. It decreased the IP activity by 100.0%. Its first patent ever was published in 2015. It filed its patents most often in United States, China and EPO (European Patent Office). Its main competitors in its focus markets computer technology, semiconductors and control are PROGRAMMABLE SILICON SOLUTIONS, HIGGS OPL CAPITAL LLC and DRESDEN MIKROELEKTRONIK.

Patent filings in countries

World map showing KILOPASS TECH INCs patent filings in countries

Patent filings per year

Chart showing KILOPASS TECH INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Luan Harry 53
#2 Cheng Charlie 50
#3 Axelrad Valery 46
#4 Bateman Bruce L 24
#5 Bateman Bruce 21
#6 Chevallier Christophe J 10
#7 Chevallier Christophe 10
#8 Ong Adrian E 8
#9 Bill Colin Stewart 4
#10 Su Tao 3

Latest patents

Publication Filing date Title
WO2018089559A1 Vertical thyristor cell and memory array with silicon germanium base regions
US2018102161A1 Vertical Thyristor Memory Array and Memory Array Tile Therefor
US2018102160A1 DDR Controller for Thyristor Memory Cell Arrays
US2018053766A1 High density vertical thyristor memory cell array with improved isolation
EP3255670A1 Three-transistor otp memory cell
EP3203517A1 Methods and systems for reducing electrical disturb effects between thyristor memory cells using heterostructured cathodes
US9754641B1 Tunable sense amplifier reference for single-ended bit lines
US2017352665A1 Thyristor memory cell with assist device
US2018102159A1 Memory disturb recovery scheme for cross-point memory arrays
US9842639B1 Systems and methods for managing read voltages in a cross-point memory array
US9646671B1 Systems and methods for managing write voltages in a cross-point memory array
US9653151B1 Memory array having segmented row addressed page registers
US2018101190A1 Voltage reference circuits with programmable temperature slope and independent offset control
US2018096730A1 High-speed differential current sensing of preprogrammed NVM cells
US9696744B1 CMOS low voltage bandgap reference design with orthogonal output voltage trimming
US2016329094A1 Methods of reading six-transistor cross-coupled thyristor-based SRAM memory cells
US2017229464A1 Methods and systems for reducing electrical disturb effects between thyristor memory cells using heterostructured cathodes
US2016379984A1 Thyristor Memory Cell with Gate in Trench Adjacent the Thyristor
US2017011781A1 Semiconductor memory sensing architecture
US2016379720A1 Write enhancement for one time programmable (OTP) semiconductors