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Memory device having 2-transistor vertical memory cell and a common plate
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Memory device having 2-transistor vertical memory cell and shield structures
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Memory device having 2-transistor vertical memory cell and a common plate
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Memory device having shared read/write data line for 2-transistor vertical memory cell
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Single word line gain cell with complementary read write channel
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Vertical 2-transistor memory cell
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Arrays of vertically-oriented transistors, and memory arrays including vertically-oriented transistors
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Memory cells having capacitor dielectric directly against a transistor source/drain region
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