|
US2011119452A1
|
|
Hybrid transactional memory system (HybridTM) and method
|
|
US2011119508A1
|
|
Power efficient stack of multicore microprocessors
|
|
US2011055483A1
|
|
Transactional memory system with efficient cache support
|
|
US2011055831A1
|
|
Program execution with improved power efficiency
|
|
US2010217868A1
|
|
Microprocessor with software control over allocation of shared resources among multiple virtual servers
|
|
US2008288238A1
|
|
Computing system with guest code support of transactional memory
|
|
US2009113443A1
|
|
Transactional memory computing system with support for chained transactions
|
|
US2008288730A1
|
|
Transactional memory system which employs thread assists using address history tables
|
|
US2008288819A1
|
|
Computing system with transactional memory using millicode assists
|
|
US2008288726A1
|
|
Transactional memory system with fast processing of common conflicts
|
