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Recessed channel with separated ONO memory device
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Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance
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Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device
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Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device
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Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen
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Memory device having high work function gate and method of erasing same
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Non-volatile memory read circuit with end of life simulation
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Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference
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Method of formation of semiconductor resistant to hot carrier injection stress
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ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices
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ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices
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Memory with improved charge-trapping dielectric layer
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Ground structure for page read and page write for flash memory
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Dummy wordline for erase and bitline leakage
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Salicided gate for virtual ground arrays
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Liner for semiconductor memories and manufacturing method therefor
