CHIDAMBARRAO DURESETI has a total of 18 patent applications. Its first patent ever was published in 2005. It filed its patents most often in United States and WIPO (World Intellectual Property Organization). Its main competitors in its focus markets semiconductors, computer technology and micro-structure and nano-technology are PARADIGM TECHNOLOGY INC, INTELLIGENT SOURCES DEV CORP and SHAH UDAY.
# | Country | Total Patents | |
---|---|---|---|
#1 | United States | 17 | |
#2 | WIPO (World Intellectual Property Organization) | 1 |
# | Industry | |
---|---|---|
#1 | Semiconductors | |
#2 | Computer technology | |
#3 | Micro-structure and nano-technology | |
#4 | Machines |
# | Technology | |
---|---|---|
#1 | Semiconductor devices | |
#2 | Electric digital data processing | |
#3 | Nanostructure applications | |
#4 | Unspecified technologies |
# | Name | Total Patents |
---|---|---|
#1 | Chidambarrao Dureseti | 18 |
#2 | Liang Yue | 3 |
#3 | Mccullen Judith H | 3 |
#4 | Yu Xiaojun | 3 |
#5 | Sekaric Lidija | 3 |
#6 | Dokumaci Omer H | 3 |
#7 | Gluschenkov Oleg G | 2 |
#8 | Narasimha Shreesh | 2 |
#9 | Yuan Jun | 2 |
#10 | Williams Richard Q | 2 |
Publication | Filing date | Title |
---|---|---|
US8476706B1 | Cmos having a sic/sige alloy stack | |
US2012261672A1 | Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers | |
US2012054711A1 | Circuit analysis using transverse buckets | |
US2011163385A1 | Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same | |
US2010252800A1 | Nanowire devices for enhancing mobility through stress engineering | |
US2010032846A1 | IC having viabar interconnection and related method | |
US2009178012A1 | Methodology for improving device performance prediction from effects of active area corner rounding | |
US2006273393A1 | Field effect transistor having multiple conduction states |