|
US10992449B1
|
|
Encoding and striping technique for DC balancing in single-ended signaling
|
|
US10922469B1
|
|
Methods and systems of enabling concurrent editing of hierarchical electronic circuit layouts
|
|
US10963610B1
|
|
Analyzing clock jitter using delay calculation engine
|
|
US10922456B1
|
|
Circuit modification for efficient electro-static discharge analysis of integrated circuits
|
|
US10936776B1
|
|
Analyzing waveform data generated for simulated circuit design
|
|
US10885252B1
|
|
Coverage model enhancement to support logic and arithmetic expressions
|
|
US10929589B1
|
|
Generating routing structure for clock network based on edge intersection detection
|
|
US10990733B1
|
|
Shared timing graph propagation for multi-mode multi-corner static timing analysis
|
|
US10958484B1
|
|
Time-based decision feedback equalizer
|
|
US10944397B1
|
|
Compact four-terminal TCOIL
|
|
US10936777B1
|
|
Unified improvement scoring calculation for rebuffering an integrated circuit design
|
|
US10949596B1
|
|
System, method, and computer program product for simultaneous routing and placement in an electronic circuit design
|
|
US10977408B1
|
|
Systems and methods of concurrent placement of input-output pins and internal components in an integrated circuit design
|
|
US10936783B1
|
|
Runtime efficient circuit placement search location selection
|
|
US10963618B1
|
|
Multi-dimension clock gate design in clock tree synthesis
|
|
US10963617B1
|
|
Modifying route topology to fix clock tree violations
|
|
US10963620B1
|
|
Buffer insertion technique to consider edge spacing and stack via design rules
|
|
US10885250B1
|
|
Clock gate placement with data path awareness
|
|
US10860764B1
|
|
Layer assignment technique to improve timing in integrated circuit design
|
|
US10963616B1
|
|
Systems and methods of aligning sets of wires with minimum spacing rules
|
