US2015379186A1
|
|
System and method for grading and selecting simulation tests using property coverage
|
US2015234973A1
|
|
System and method for abstraction of a circuit portion of an integrated circuit
|
US2014047399A1
|
|
System and method for inferring higher level descriptions from RTL topology based on naming similarities and dependency
|
US8839171B1
|
|
Method of global design closure at top level and driving of downstream implementation flow
|
US8732647B1
|
|
Method for creating physical connections in 3D integrated circuits
|
US8782582B1
|
|
Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis
|
US8745567B1
|
|
Efficient apparatus and method for analysis of RTL structures that cause physical congestion
|
US2013246989A1
|
|
System and method for metastability verification of circuits of an integrated circuit
|
US2014282322A1
|
|
System and method for filtration of error reports respective of static and quasi-static signals within an integrated circuit design
|
US2014282321A1
|
|
System and method for a hybrid clock domain crossing verification
|
US8806401B1
|
|
System and methods for reasonable functional verification of an integrated circuit design
|
US2014282338A1
|
|
System and method for altering circuit design hierarchy to optimize routing and power distribution using initial RTL-level circuit description netlist
|
US8635578B1
|
|
System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption
|
US8656328B1
|
|
System and method for abstraction of a circuit portion of an integrated circuit
|
US2014250414A1
|
|
Method for measuring assertion density in a system of verifying integrated circuit design
|
US8656326B1
|
|
Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design
|
US8739087B1
|
|
System and method for large multiplexer identification and creation in a design of an integrated circuit
|
US2014033155A1
|
|
Systems and methods for generating a higher level description of a circuit design based on connectivity strengths
|
US8533647B1
|
|
Method for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design
|
US2014089879A1
|
|
Characterization based buffering and sizing for system performance optimization
|