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ATRENTA INC

Overview
  • Total Patents
    44
  • GoodIP Patent Rank
    225,750
About

ATRENTA INC has a total of 44 patent applications. Its first patent ever was published in 2002. It filed its patents most often in United States. Its main competitors in its focus markets computer technology, measurement and environmental technology are STELLAR COMPUTER, ZIPALOG INC and ODA YASUO.

Patent filings in countries

World map showing ATRENTA INCs patent filings in countries
# Country Total Patents
#1 United States 44

Patent filings per year

Chart showing ATRENTA INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Movahed-Ezazi Mohammad H 9
#2 Rahim Solaiman 7
#3 Sarwary Mohamed Shaker 6
#4 Murphy Bernard 6
#5 Kapoor Bhanu 5
#6 Mneimneh Maher 4
#7 Nayak Anshuman 4
#8 Chakrabarti Samantak 4
#9 Sarwary Shaker 4
#10 Bagchi Debabrata 4

Latest patents

Publication Filing date Title
US2015379186A1 System and method for grading and selecting simulation tests using property coverage
US2015234973A1 System and method for abstraction of a circuit portion of an integrated circuit
US2014047399A1 System and method for inferring higher level descriptions from RTL topology based on naming similarities and dependency
US8839171B1 Method of global design closure at top level and driving of downstream implementation flow
US8732647B1 Method for creating physical connections in 3D integrated circuits
US8782582B1 Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis
US8745567B1 Efficient apparatus and method for analysis of RTL structures that cause physical congestion
US2013246989A1 System and method for metastability verification of circuits of an integrated circuit
US2014282322A1 System and method for filtration of error reports respective of static and quasi-static signals within an integrated circuit design
US2014282321A1 System and method for a hybrid clock domain crossing verification
US8806401B1 System and methods for reasonable functional verification of an integrated circuit design
US2014282338A1 System and method for altering circuit design hierarchy to optimize routing and power distribution using initial RTL-level circuit description netlist
US8635578B1 System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption
US8656328B1 System and method for abstraction of a circuit portion of an integrated circuit
US2014250414A1 Method for measuring assertion density in a system of verifying integrated circuit design
US8656326B1 Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design
US8739087B1 System and method for large multiplexer identification and creation in a design of an integrated circuit
US2014033155A1 Systems and methods for generating a higher level description of a circuit design based on connectivity strengths
US8533647B1 Method for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design
US2014089879A1 Characterization based buffering and sizing for system performance optimization