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Processor instruction used to determine whether to perform a memory-related trap
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Accelerated class check
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Array access
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Testing replicated sub-systems in a yield-enhancing chip-test environment using on-chip compare to expected results for parallel scan chains testing critical and repairable sections of each sub-system
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Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory module
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Segmented virtual machine transport mechanism
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Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines
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Speculative multiaddress atomicity
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Error recovery of variable-length packets without sequence numbers or special symbols used for synchronizing transmit retry-buffer pointer
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System and method for concurrent compacting self pacing garbage collection using loaded value and access barriers
