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ALLIANCE SEMICONDUCTOR CORP

Overview
  • Total Patents
    74
About

ALLIANCE SEMICONDUCTOR CORP has a total of 74 patent applications. Its first patent ever was published in 1992. It filed its patents most often in United States and WIPO (World Intellectual Property Organization). Its main competitors in its focus markets computer technology, semiconductors and audio-visual technology are ETRON TECHNOLOGY INC, EOREX CORP and TAKAHASHI YASUYUKI.

Patent filings in countries

World map showing ALLIANCE SEMICONDUCTOR CORPs patent filings in countries

Patent filings per year

Chart showing ALLIANCE SEMICONDUCTOR CORPs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Reddy Chitranjan N 39
#2 Shrivastava Ritu 15
#3 Greene Spencer H 9
#4 Kengeri Subramani 8
#5 Medhekar Ajit K 8
#6 Poteet Kenneth A 7
#7 Stephens Jr Michael C 5
#8 Ray Abhijit 4
#9 Daniel Andrew 4
#10 Daniel Andrew D 4

Latest patents

Publication Filing date Title
US2003112816A1 Recoverable cut-through buffer and method
US2001040581A1 Shared memory graphics accelerator system
US6476666B1 Bootstrapped charge pump
US7027548B1 Delay settings for a wide-range, high-precision delay-locked loop and a delay locked loop implementation using these settings
US6589834B1 Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current
US6738917B2 Low latency synchronization of asynchronous data
US6303959B1 Semiconductor device having reduced source leakage during source erase
US6137746A High performance random access memory with multiple local I/O lines
US6108250A Fast redundancy scheme for high density, high speed memories
US6258714B1 Self-aligned contacts for salicided MOS devices
US6141236A Interleaved stitch using segmented word lines
US6016270A Flash memory architecture that utilizes a time-shared address bus scheme and separate memory cell access paths for simultaneous read/write operations
US6301629B1 High speed/low speed interface with prediction cache
US6292416B1 Apparatus and method of reducing the pre-charge time of bit lines in a random access memory
US6020237A Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures
US6157587A Data sense arrangement for random access memory
US5777631A Method and apparatus for displaying a video window in a computer graphics display
US6175520B1 Nonvolatile memory array having local program load line repeaters
US6392267B1 Flash EPROM array with self-aligned source contacts and programmable sector erase architecture
US5929872A Method and apparatus for multiple compositing of source data in a graphics display processor