|
US2020286559A1
|
|
Seu stabilized memory cells
|
|
US2020242190A1
|
|
Apparatus and method for combining analog neural net with fpga routing in a monolithic integrated circuit
|
|
US2019229734A1
|
|
Vertical resistor buffered multiplexer buskeeper
|
|
US2019237139A1
|
|
Hybrid configuration memory cell
|
|
US2019228825A1
|
|
Vertical resistor based sram cells
|
|
US2020150925A1
|
|
FPGA logic cell with improved support for counters
|
|
US2019221259A1
|
|
FPGA configuration cell utilizing NVM technology and redundancy
|
|
US2019190424A1
|
|
Apparatus and method for sensorless detection of load torque of a stepper motor and for optimizing drive current for efficient operation
|
|
US2019172522A1
|
|
SRAM configuration cell for low-power field programmable gate arrays
|
|
US2019172756A1
|
|
Hybrid high-voltage low-voltage finfet device
|
|
US2019190522A1
|
|
FPGA math block with dedicated connections
|
|
US2019165788A1
|
|
Efficient lookup table modules for user-programmable integrated circuits
|
|
US2020006429A1
|
|
Circuit and layout for resistive random-access memory arrays having two bit lines per column
|
|
US2020006430A1
|
|
Circuit and layout for resistive random-access memory arrays
|
|
CN111033624A
|
|
Circuit and method for programming a resistive random access memory device
|
|
US2018164351A1
|
|
Power supply glitch detector
|
|
CN110036484A
|
|
Resistor random access memory cell
|
|
US2018108409A1
|
|
Circuits and methods for preventing over-programming of ReRAM-based memory cells
|
|
US2017346426A1
|
|
Apparatus and method to detect stall condition of a stepper motor
|
|
US2017161224A1
|
|
Apparatus and methods for in-application programming of flash-based programmable logic devices
|
