Learn more

3D PLUS

Overview
  • Total Patents
    118
  • GoodIP Patent Rank
    26,040
  • Filing trend
    ⇩ 90.0%
About

3D PLUS has a total of 118 patent applications. It decreased the IP activity by 90.0%. Its first patent ever was published in 2000. It filed its patents most often in EPO (European Patent Office), WIPO (World Intellectual Property Organization) and France. Its main competitors in its focus markets semiconductors, audio-visual technology and machines are EUPEC GMBH & CO KG, KANTO SANYO SEMICONDUCTORS CO and DAWNING LEADING TECHNOLOGY INC.

Patent filings per year

Chart showing 3D PLUSs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Val Christian 85
#2 Val Alexandre 9
#3 Lignier Olivier 9
#4 Dubus Patrick 8
#5 Perrot Nicolas 8
#6 Boussadia Mohamed 7
#7 Gambart Didier 4
#8 Bocage Regis 4
#9 Soufflet Fabrice 4
#10 Couderc Pascal 4

Latest patents

Publication Filing date Title
FR3092213A1 series resonant power converter
FR3083324A1 ELECTRONIC COMPONENT DEVERMINING EQUIPMENT
FR3077825A1 METHOD FOR METALLIZING HOLES OF AN ELECTRONIC MODULE BY LIQUID PHASE DEPOSITION
KR20190093629A Pseudo-resonant buck-type converter with continuous high frequency voltage
US2018172504A1 3D imaging optoelectronic module
US2017372935A1 Method of collective fabrication of 3D electronic modules configured to operate at more than 1 GHz
FR3048123A1 METHOD FOR INTERCONNECTING CHIP ON CHIP MINIATURIZED FROM A 3D ELECTRONIC MODULE
EP3059763A1 Method for manufacturing a 3d electronic module with external interconnection leads
FR3038130A1 3D ELECTRONIC MODULE COMPRISING A STACK OF BALL CASES
FR3034253A1 ELECTRONIC CHIP DEVICE WITH IMPROVED THERMAL RESISTANCE AND METHOD OF MANUFACTURING THE SAME
EP2610906A1 Method for collective production of 3D electronic modules comprising only valid PCBs
FR2974942A1 PROCESS FOR PRODUCING RECONSTITUTED PLATES WITH THE MAINTENANCE OF CHIPS DURING THEIR ENCAPSULATION
WO2010142804A1 Method for positioning chips during the production of a reconstituted wafer
KR20110134467A Method for positioning chips during the production of a reconstituted board
US2011247210A1 Process for the wafer-scale fabrication of electronic modules for surface mounting
EP2053646A1 Method for vertical interconnection inside 3D electronic modules using vias
EP2126969A1 Method of interconnecting electronic wafers
WO2008022901A2 Process for the collective manufacturing of electronic 3d modules
US2008289174A1 Process for the collective fabrication of 3D electronic modules
WO2007063113A1 3d electronic module