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Radio frequency DAC with improved linearity using shadow capacitor switching
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Post-synthesis insertion of debug cores
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Redundancy scheme for multi-chip stacked devices
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Digital fractional clock synthesizer with period modulation
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Efuse bank and associated anchor bits
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Dynamic scan chain and method
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Hybrid multiplying capacitive digital-to-analog converter (MC-DAC) based loop regulation
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Programmable pipeline at interface of hardened blocks
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Data flow graph optimization techniques for RTL loops with conditional-exit statements
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