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Novel testability structure of lookup table
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FPGA time sequence parameter extraction method
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Novel FPGA chip layout optimization method
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FPGA layout legalization method based on maximum flow algorithm
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Force guiding layout method for carrying out crowded area expansion based on maximum flow algorithm
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FPGA layout legalization method utilizing regional re-layout
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FPGA wiring method for improving wiring speed based on port exchange technology
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Multi-die FPGA with interconnection test function
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FPGA device with power-on reset signal waveform adjustable function
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Multi-die FPGA with silicon connection layer provided with configurable circuit
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Multi-die FPGA with real-time monitoring and configuration information correcting functions
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Multi-die FPGA for realizing system monitoring by utilizing active silicon connection layer
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Multi-die FPGA for integrating HBM memory dies by utilizing silicon connection layer
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FPGA device internally integrating network-on-chip with different bit width connecting lines
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Universal multi-die silicon stacking interconnection structure
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Multi-die silicon stacking interconnection structure FPGA
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Silicon connection layer test circuit for testing by using test bare chip
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Multi-bare-chip FPGA (field programmable Gate array) formed based on silicon connection layer with universal structure
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Multi-die FPGA for integrating multi-die network-on-chip using silicon connection layer
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Multi-die FPGA for implementing clock tree by using active silicon connection layer
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