|
US2016142057A1
|
|
Compact logic evaluation gates using null convention
|
|
US2016125118A1
|
|
Computing resource allocation based on flow graph translation
|
|
WO2015066561A1
|
|
Logical elements with switchable connections
|
|
US2015076564A1
|
|
Multi-threshold circuitry based on silicon-on-insulator technology
|
|
US2014181164A1
|
|
Selectively combinable shifters
|
|
US2014164457A1
|
|
Extensible iterative multiplier
|
|
US2014049288A1
|
|
Hum generation circuitry
|
|
US2013249594A1
|
|
Implementation method for fast NCL data path
|
|
US2013214814A1
|
|
Self-ready flash null convention logic
|
|
US2013214813A1
|
|
Multi-threshold flash NCL circuitry
|
|
US2008059773A1
|
|
Systems and methods using an invocation model of process expression
|
