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GB201201580D0
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A high data rate SerDes receiver arranged to receive input from a low data rate SerDes transmitter
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GB201201610D0
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A clock phase interpolator with independent quadrant rotation
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GB201201589D0
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Multiplexing streams on to faster serial lanes for power saving, wherein stream synchronisation characters are replaced with stream identifiers
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GB201201581D0
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Automatic gain control in a data receiver
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GB201201584D0
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Optimising parameters in a data receiver using data waveform eye height measurements
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GB201201596D0
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Multi-lane alignment and de-skew circuit and algorithm
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GB201201611D0
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An octal clock phase interpolator
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GB201201604D0
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Improved loop filter for phase locked loop (PLL)
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GB201201606D0
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Fast start-up circuit for phase locked loop (PLL)
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GB201201377D0
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Method of processing data samples and circus therefor
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GB201120505D0
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Power efficient high swing long reach transmitter architecture
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GB201120519D0
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Improvements in or relating to feed forward equilisation
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GB201106360D0
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Data slicing level and timing adjustment
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GB201020084D0
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Pattern based timing recovery system
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GB201006715D0
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Improvements in or relating to feed forward equalisation
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EP2378727A1
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Channel equalization using application specific digital signal processing in high-speed digital transmission systems
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GB201006023D0
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Improvements in or relating to clock recovery
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GB201003857D0
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Power efficent high swing long reach transmitter architecture
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GB201003214D0
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Improvements in or relating to resetting across multiple clock domains
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GB201003215D0
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Improvements in or relating to multiplexers
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