Learn more

SYNTEST TECHNOLOGIES INC

Overview
  • Total Patents
    79
  • GoodIP Patent Rank
    200,782
About

SYNTEST TECHNOLOGIES INC has a total of 79 patent applications. Its first patent ever was published in 2002. It filed its patents most often in United States, WIPO (World Intellectual Property Organization) and EPO (European Patent Office). Its main competitors in its focus markets measurement and computer technology are JTAG TECHNOLOGIES BV, VERISITY LTD and BEIJING CHIPADVANCED CO LTD.

Patent filings in countries

World map showing SYNTEST TECHNOLOGIES INCs patent filings in countries
# Country Total Patents
#1 United States 46
#2 WIPO (World Intellectual Property Organization) 15
#3 EPO (European Patent Office) 11
#4 China 3
#5 Australia 2
#6 Japan 2

Patent filings per year

Chart showing SYNTEST TECHNOLOGIES INCs patent filings per year from 1900 to 2020

Focus industries

# Industry
#1 Measurement
#2 Computer technology

Top inventors

# Name Total Patents
#1 Wen Xiaoqing 54
#2 Wang Laung-Terng 40
#3 Wang Hsin-Po 34
#4 Wang Laung-Terng L-T 34
#5 Abdel-Hafez Khader S 31
#6 Lin Shyh-Horng 26
#7 Lin Meng-Chyi 25
#8 Kao Shih-Chia 24
#9 Hsu Po-Ching 23
#10 Sheu Boryau Jack 19

Latest patents

Publication Filing date Title
US2014082446A1 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
US2013326281A1 X-Tracer: A Reconfigurable X-Tolerance Trace Compressor for Silicon Debug
US2013268818A1 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
US2011047426A1 Method and apparatus for low-pin-count scan compression
US2009235132A1 Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
US2009303815A1 Apparatus for redundancy reconfiguration of faculty memories
US7925947B1 X-canceling multiple-input signature register (MISR) for compacting output responses with unknowns
US7779322B1 Compacting test responses using X-driven compactor
US7945833B1 Method and apparatus for pipelined scan compression
US2006242502A1 Method and apparatus for broadcasting test patterns in a scan based integrated circuit
US2006059395A1 IEEE Std. 1149.4 compatible analog BIST methodology
US7210082B1 Method for performing ATPG and fault simulation in a scan-based integrated circuit
US2006064614A1 Method and apparatus for pipelined scan compression
US2005268194A1 Method and apparatus for multi-level scan compression
US7412672B1 Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
US7512851B2 Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit
US7032148B2 Mask network design for scan-based integrated circuits
WO2004107402A2 Smart capture for atpg (automatic test pattern generation) and fault simulation of scan-based integrated circuits
US2005262409A1 Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits
US7058869B2 Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits