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BEIJING CHIPADVANCED CO LTD

Overview
  • Total Patents
    21
  • GoodIP Patent Rank
    83,743
  • Filing trend
    ⇩ 100.0%
About

BEIJING CHIPADVANCED CO LTD has a total of 21 patent applications. It decreased the IP activity by 100.0%. Its first patent ever was published in 2013. It filed its patents most often in China. Its main competitors in its focus markets measurement, computer technology and environmental technology are SYNTEST TECHNOLOGIES INC, JTAG TECHNOLOGIES BV and TESEDA CORP.

Patent filings in countries

World map showing BEIJING CHIPADVANCED CO LTDs patent filings in countries
# Country Total Patents
#1 China 21

Patent filings per year

Chart showing BEIJING CHIPADVANCED CO LTDs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Shi Zhigang 13
#2 Zhou Naixin 6
#3 Jin Lan 4
#4 Yang Yingchao 4
#5 Sun Xin 4
#6 He Chao 3
#7 Liu Wei 3
#8 Li Liang 3
#9 Wu Ping 3
#10 Yang Zhenyu 3

Latest patents

Publication Filing date Title
CN111435146A Wafer testing method and system based on MES
CN111435308A Method and device for acquiring program name of probe station
CN111435145A Test system for smart card chip
CN109935535A A kind of wafer device for dotting
CN109901650A A kind of a reference source method for repairing and regulating of embedded flash chip
CN109814922A A kind of method and system that wafer Map file is converted to ten piece files
CN109818622A A kind of method and apparatus of pair of flash chip coding
CN107340487A A kind of method checked test system and be in actual processing ability under stable state
CN106546937A A kind of validated measurement systems whether in steady statue method
CN107543944A A kind of high current monitoring method of integrated circuit test system
CN106872872A A kind of chip testing vector conversion method
CN106814299A A kind of anti-interference method of digital-analog mix-mode chip test
CN106709099A Method for converting MAP file of probe station
CN106483444A The method preventing wafer Map figure displacement using test program
CN106483443A A kind of method preventing wafer Map figure displacement
CN105891696A Integrated-circuit low-temperature test method
CN105656642A Method for realizing authority management of integrated circuit test management system with INI
CN105893000A Method for preventing system time of test machine from being illegally modified
CN105527940A Method for realizing flow control of test management system via INI file
CN104715101A Automatic generating method for pick-up file in wafer testing process