| # | Country | Total Patents | |
|---|---|---|---|
| #1 | Taiwan | 4 | |
| #2 | United States | 4 | |
| #3 | Australia | 3 | |
| #4 | EPO (European Patent Office) | 3 | |
| #5 | WIPO (World Intellectual Property Organization) | 3 | |
| #6 | Japan | 1 |
| # | Industry | |
|---|---|---|
| #1 | Computer technology | |
| #2 | Audio-visual technology | |
| #3 | Semiconductors | |
| #4 | Measurement |
| # | Technology | |
|---|---|---|
| #1 | Electric digital data processing | |
| #2 | Special information storage | |
| #3 | Measuring electric variables | |
| #4 | Semiconductor devices |
| # | Name | Total Patents |
|---|---|---|
| #1 | Teig Steven | 8 |
| #2 | Ganley Joseph L | 4 |
| #3 | Li Jun | 4 |
| #4 | Frankle Jonathan A | 4 |
| #5 | Jacques Etienne | 4 |
| #6 | Buset Oscar | 4 |
| #7 | Zhao Hong | 4 |
| #8 | Chiu Hsien-Yen | 4 |
| #9 | Caldwell Andrew | 4 |
| #10 | Chao Heng-Yi | 3 |
| Publication | Filing date | Title |
|---|---|---|
| WO0247165A2 | Method and apparatus for considering diagonal wiring in placement | |
| AU8638401A | High accuracy timing model for integrated circuit verification | |
| US6480986B1 | IC substrate noise modeling including extracted capacitance for improved accuracy | |
| US6291324B1 | Method of modeling IC substrate noises utilizing improved doping profile access | |
| US6438733B1 | IC substrate noise modeling with improved surface gridding technique | |
| US5999010A | Method of measuring interconnect coupling capacitance in an IC chip |