| # | Country | Total Patents | |
|---|---|---|---|
| #1 | WIPO (World Intellectual Property Organization) | 5 | |
| #2 | United States | 4 | |
| #3 | EPO (European Patent Office) | 3 | |
| #4 | Taiwan | 2 |
| # | Industry | |
|---|---|---|
| #1 | Semiconductors | |
| #2 | Machines | |
| #3 | Machine tools |
| # | Technology | |
|---|---|---|
| #1 | Semiconductor devices | |
| #2 | Unspecified technologies | |
| #3 | Grinding or polishing devices |
| # | Name | Total Patents |
|---|---|---|
| #1 | Craven Robert A | 9 |
| #2 | Iyer Subramanian S | 8 |
| #3 | Bartram Ronald D | 4 |
| #4 | Golland David I | 4 |
| #5 | Downey William P | 3 |
| #6 | Baran Emil | 3 |
| #7 | Mastroianni Mark L | 3 |
| #8 | Lawrence Edwin | 2 |
| #9 | Dimilia David | 2 |
| #10 | Bansal Iqbal K | 1 |
| Publication | Filing date | Title |
|---|---|---|
| US5948699A | Wafer backing insert for free mount semiconductor polishing apparatus and process | |
| WO9809804A1 | Flattening process for bonded semiconductor substrates | |
| WO9727621A1 | Selective-etch edge trimming process for manufacturing semiconductor-on-insulator wafers | |
| US5937312A | Single-etch stop process for the manufacture of silicon-on-insulator wafers | |
| US5668045A | Process for stripping outer edge of BESOI wafers |