|
EP1886240A2
|
|
System and method for analyzing power consumption of electronic design undergoing emulation or hardware based on simulation acceleration
|
|
US2006230251A1
|
|
System and method for providing compact mapping between dissimilar memory systems
|
|
US2007219772A1
|
|
Method and apparatus for rewinding emulated memory circuits
|
|
US2006190237A1
|
|
Emulation processor interconnection architecture
|
|
US2005267728A1
|
|
System and method for validating an input/output voltage of a target system
|
|
US2005267729A1
|
|
Extensible memory architecture and communication protocol for supporting multiple devices in low-bandwidth, asynchronous applications
|
|
US2005267727A1
|
|
System and method for providing flexible signal routing and timing
|
|
US2005278163A1
|
|
System and method for resolving artifacts in differential signals
|
|
US2005267730A1
|
|
Dynamic programming of trigger conditions in hardware emulation systems
|
|
US2006190239A1
|
|
Method and system for hardware based reporting of assertion information for emulation and hardware acceleration
|
|
US2005266709A1
|
|
System and method for ejecting a high extraction force electromechanical connector
|
|
US2005271078A1
|
|
System and method for configuring communication systems
|
|
US2005265375A1
|
|
System and method for identifying target systems
|
|
US7356455B2
|
|
Optimized interface for simulation and visualization data transfer between an emulation system and a simulator
|
|
US2004123258A1
|
|
Logic multiprocessor for FPGA implementation
|
|
US2004148153A1
|
|
Memory rewind and reconstruction for hardware emulator
|
|
US2003171908A1
|
|
Simulation and timing control for hardware accelerated simulation
|
|
US2003084414A1
|
|
Timing resynthesis in a multi-clock emulation system
|
|
WO0241167A2
|
|
Method and apparatus for dynamically testing electrical interconnect
|
|
US2002049578A1
|
|
Hardware-assisted design verification system using a packet-based protocol logic synthesized for efficient data loading and unloading
|
