IKOS SYSTEMS INC has a total of 14 patent applications. Its first patent ever was published in 1986. It filed its patents most often in United States, EPO (European Patent Office) and Australia. Its main competitors in its focus markets computer technology, measurement and basic communication technologies are MAGIMA DIGITAL INFORMATION CO, QUICKTURN DESIGN SYSTEMS INC and Breker Verification Systems.
# | Country | Total Patents | |
---|---|---|---|
#1 | United States | 9 | |
#2 | EPO (European Patent Office) | 3 | |
#3 | Australia | 1 | |
#4 | WIPO (World Intellectual Property Organization) | 1 |
# | Industry | |
---|---|---|
#1 | Computer technology | |
#2 | Measurement | |
#3 | Basic communication technologies |
# | Technology | |
---|---|---|
#1 | Electric digital data processing | |
#2 | Measuring electric variables | |
#3 | Pulse technique |
# | Name | Total Patents |
---|---|---|
#1 | Stewart William K | 5 |
#2 | Selvidge Charles W | 4 |
#3 | Goode Terry Lee | 3 |
#4 | Hafeman Dan R | 3 |
#5 | Fazakerly William | 3 |
#6 | Seneski Mark | 2 |
#7 | Kudlugi Muralidhar R | 2 |
#8 | Crouch Ken | 2 |
#9 | Wong Marina | 2 |
#10 | Nei Chu C | 2 |
Publication | Filing date | Title |
---|---|---|
US6223148B1 | Logic analysis system for logic emulation systems | |
US6061511A | Reconstruction engine for a hardware circuit emulator | |
US6009531A | Transition analysis and circuit resynthesis method and device for digital circuit modeling | |
US6104210A | Method for avoiding bus contention in a digital circuit | |
US5854752A | Circuit partitioning technique for use with multiplexed inter-connections | |
US5126966A | High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs | |
US4787062A | Glitch detection by forcing the output of a simulated logic device to an undefined state | |
US4787061A | Dual delay mode pipelined logic simulator |