Integrated circuit for use in e.g. electronic system, has interface-structures directly connected to doped area in respective partial areas of contact surface, where structures are made from respective conducting materials
DE102009059156A1
Solar cell, has rearside conductor rails provided on lower side of substrate and arranged parallel to emitter-conductor rails, where emitter and rearside conductor rails are inclined with respect to solar cell edge at preset angle
DE102009054630A1
Method for producing a photovoltaic device
DE102009054003A1
Integrated circuit for use as e.g. conductive bridge RAM in data processing system, which is utilized for e.g. cellular communication, has voltage limitation-switching network limiting voltage, when circuit is found in read mode
DE102009054004A1
Integrated circuit for use with condenser, has lower electrode arranged over semiconductor body, where lower electrode has base region, top region and outer side panel
US2011034045A1
Stacking Technique for Circuit Devices
US2009213648A1
Integrated circuit comprising a thyristor and method of controlling a memory cell comprising a thyristor
DE102008059015A1
Method for managing data stream i.e. digital data stream, in communication system, involves calculating scanning value in position, and calculating another position by former position, where valid value is read in former position
DE102008058615A1
Integrated circuit with buffer capacities
US2010127746A1
Digitally controlled CML buffer
DE102008057411A1
Method and device for monitoring a storage device
DE102008056385A1
Memory chip has multiple memory cells, which have data path with switching element for interconnecting output data signals and temperature sensor for determining memory chip temperature
US2010110753A1
Ferroelectric Memory Cell Arrays and Method of Operating the Same
DE102008053432B3
Contact base for integrated circuit, has connector for mechanical contact of contact base on module carrier, where contact element is electrically connected to module carrier
DE102008052944A1
Multi-chip memory, device and multi-chip memory stacks
US2010097874A1
Method and apparatus for performing internal hidden refreshes while latching read/write commands, address and data information for later operation
DE102008052466A1
Storage system with extended storage density capability
US2010096669A1
Memory cell array comprising wiggled bit lines
DE102008051746A1
Integrated circuit with doped semiconductor line with conductive cladding
