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WO2020191273A1
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Fast equalization for jitter mitigation
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Mulit-lane synchronous reset for coherent receivers
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Sampling phase optimization for digital modulated signals
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Receiver supporting multiple data rates
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Multi-lane coherent transceiver with synchronized lane reset signals
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Dynamic constellation adaptation for slicer
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Constellation selection threshold adaptation for slicer
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On-chip voltage regulator providing extended range of voltage supplies
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High frequency digital-to-analog conversion by interleaving without return-to-zero
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Phase interpolation calibration for timing recovery
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Mitigating interaction between adaptive equalization and timing recovery
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