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Computer system that provides atomicity by using a tlb to indicate whether an exportable instruction should be executed using cache coherency or by exporting the exportable instruction, and emulates instructions specifying a bus lock
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Processor architecture having two or more floating-point status fields
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Methods and apparatus for handling and storing bi-endian words in a floating-point processor
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Method and apparatus for optimizing instruction execution
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Propagating NaNs during high precision calculations using lesser precision hardware
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High-performance processor with streaming buffer that facilitates prefetching of instructions
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Processor with apparatus for tracking prefetch and demand fetch instructions serviced by cache memory
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Apparatus and method for a load bias--load with intent to semaphore
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Method and apparatus for selectively controlling groups of registers
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Method and apparatus for constructing a stack unwind data structure
